1. Technical Field
The present invention relates generally to complementary logic circuits, and more particularly to a logic circuit that reduces energy consumption by sharing charge between complementary nodes having large capacitance prior to setting the final state of the nodes.
2. Description of the Related Art
Logic circuits in general, and storage circuits in particular, have energy consumption largely dictated by the large capacitances that must be charged and discharged to change the logic state of the signal nods. For example, in storage circuits, complementary bitlines are set to states dictated by the input or output storage value. During a state change, one of the bitlines is discharged and the other is charged, with an energy consumption equal to CV2 where C is the total capacitance of the bitlines and V is the total power supply voltage. In large arrays, both global and local bitlines are changed to provide an state change. Further, in circuits such as wide multiplexers, the select lines are also large capacitance nodes that consume large amounts of energy when their selection state is changed.
Bitlines and multiplexer selection lines, by their nature, are relatively high capacitance nodes, since they are connected to a large number of elements. The energy consumed in charging and discharging the nodes typically forms the dominant energy-consumer when a storage device is active. Since memory devices are on-par with processors today as energy-consumers in computer systems, reduction of energy consumption in memory devices is highly desirable. In processors, multiplexers are used pervasively to select between values, and are therefore operated at a very high frequency. Therefore, reduction in energy usage due changes in selection state of wide multiplexers can provide for significant reduction in energy consumption of processors and other very large-scale integrated (VLSI) logic circuits. Further, a significant portion of processor energy consumption is also involved in operation of internal storage arrays such as register files that also use bitlines, and therefore reduction in storage array energy consumption also may also provide for reduction in processor power consumption.
It is therefore desirable to provide a logic circuit and method that reduces energy consumption due to charging and/or discharging large capacitance nodes. It is further desirable to provide storage circuits and multiplexers having reduced energy consumption.